The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Jan. 31, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Feng Lin, Boise, ID (US);

Timothy M. Hollis, Meridian, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/20 (2006.01); H04L 7/00 (2006.01); H04L 25/03 (2006.01); H04L 25/49 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
H04L 25/4917 (2013.01); G11C 7/1057 (2013.01); G11C 7/1069 (2013.01); G11C 7/1084 (2013.01); G11C 7/1096 (2013.01); G11C 7/20 (2013.01); H04L 7/0037 (2013.01); H04L 25/03038 (2013.01); G11C 7/1063 (2013.01); H04L 2025/03363 (2013.01);
Abstract

A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.


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