The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Sep. 29, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Shay Gueron, Haifa, IL;

Vlad Krasnov, Nesher, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); H04L 9/06 (2006.01); G06F 9/30 (2018.01); G06F 21/60 (2013.01);
U.S. Cl.
CPC ...
H04L 9/0637 (2013.01); G06F 9/30007 (2013.01); G06F 9/30036 (2013.01); G06F 9/30156 (2013.01); G06F 21/602 (2013.01); H04L 9/0625 (2013.01); H04L 9/0631 (2013.01); H04L 2209/12 (2013.01); H04L 2209/24 (2013.01); H04L 2209/80 (2013.01);
Abstract

A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.


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