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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10446561 B1

PDFFull Text
Date of Patent:
Oct. 15, 2019

Filed:

Aug. 29, 2018

Semiconductor devices including a dummy gate structure on a fin

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Sang-Jine Park, Yongin-si, KR;

Kee-Sang Kwon, Seoul, KR;

Do-Hyoung Kim, Hwaseong-si, KR;

Bo-Un Yoon, Seoul, KR;

Keun-Hee Bai, Suwon-si, KR;

Kwang-Yong Yang, Seoul, KR;

Kyoung-Hwan Yeo, Seoul, KR;

Yong-Ho Jeon, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., , KR;

Attorney:

Myers Bigel, P.A.

Primary Examiner:

Thao P Le

Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 27/1116 (2013.01); H01L 29/06 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/7848 (2013.01);
Abstract

Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

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