The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2019
Filed:
Jun. 07, 2018
Applicant:
Qorvo Us, Inc., Greensboro, NC (US);
Inventors:
Jose Jimenez, Dallas, TX (US);
Jinqiao Xie, Allen, TX (US);
Assignee:
Qorvo US, Inc., Greensboro, NC (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 27/088 (2006.01); H01L 27/085 (2006.01); H01L 29/417 (2006.01); H01L 29/36 (2006.01); H01L 29/205 (2006.01); H01L 21/306 (2006.01); H01L 21/8252 (2006.01); H01L 21/762 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/12 (2006.01); H01L 27/06 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 27/085 (2013.01); H01L 21/0254 (2013.01); H01L 21/02458 (2013.01); H01L 21/30612 (2013.01); H01L 21/76224 (2013.01); H01L 21/8252 (2013.01); H01L 27/0605 (2013.01); H01L 29/0653 (2013.01); H01L 29/0843 (2013.01); H01L 29/1029 (2013.01); H01L 29/1075 (2013.01); H01L 29/1095 (2013.01); H01L 29/122 (2013.01); H01L 29/205 (2013.01); H01L 29/36 (2013.01); H01L 29/4175 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01); H01L 27/0883 (2013.01); H01L 29/2003 (2013.01);
Abstract
An integrated circuit die having a substrate with a first device stack disposed upon the substrate and a second device stack spaced from the first device stack and disposed upon the substrate is disclosed. The second device stack includes a first portion of a channel layer and a threshold voltage shift layer disposed between the first portion of the channel layer and the substrate, wherein the threshold voltage shift layer is configured to set a threshold voltage that is a minimum device control voltage required to create a conducting path within the first portion of the channel layer.