The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2019
Filed:
Apr. 29, 2019
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Feng Lin, Boise, ID (US);
Yuanzhong Wan, Boise, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/02 (2006.01); G11C 11/00 (2006.01); H01L 25/065 (2006.01); G11C 11/4076 (2006.01); G11C 11/4091 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 11/4076 (2013.01); G11C 11/4091 (2013.01); G11C 7/222 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01);
Abstract
Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and coupled to one another and the logic component, a plurality of memory component programmable delay lines (PDLs), of the plurality of memory component PDLs associated with a respective one of the plurality of memory components, and a logic component programmable delay line (LPDL) coupled to the logic component and each of the plurality of memory component PDLs.