The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2019
Filed:
Apr. 03, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Boyan Boyanov, Portland, OR (US);
Kanwal Jit Singh, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/485 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/7684 (2013.01); H01L 21/7685 (2013.01); H01L 21/76802 (2013.01); H01L 21/76849 (2013.01); H01L 21/76879 (2013.01); H01L 21/76883 (2013.01); H01L 23/485 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53209 (2013.01); H01L 23/53295 (2013.01); H01L 2924/0002 (2013.01);
Abstract
At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.