The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Nov. 16, 2016
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Anne Hughes, Austin, TX (US);

John MacLaren, Austin, TX (US);

Devika Raghu, Bangalore, IN;

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/406 (2006.01); G11C 11/4096 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40615 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 11/4096 (2013.01);
Abstract

A system and method are provided for system for adaptive refresh of a memory device having multiple integrated circuit chips. A command generation portion generates commands for actuating a plurality of operational tasks on the memory device, including at least read, write, and refresh operations for selectively addressed storage cells of the memory device. A command management portion stores the commands and selects from the commands for timely execution of corresponding operational tasks on the memory device. A refresh management portion coupled to the command generation and command management portions actuates a plurality of refresh operations adaptively interleaved with other operational tasks, such that recursive refresh of the storage cells is carried out for the memory device within a predetermined refresh window of time. The refresh management portion selectively actuates each refresh operation for a chip-based selection of storage cells, whereby the storage cells of a selected chip are refreshed.


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