The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Jun. 02, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Robert M. Toth, Lund, SE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 19/00 (2011.01); G09G 5/36 (2006.01); G06F 3/147 (2006.01); G09G 5/14 (2006.01); G06T 19/20 (2011.01);
U.S. Cl.
CPC ...
G09G 5/363 (2013.01); G06F 3/147 (2013.01); G06T 19/006 (2013.01); G06T 19/20 (2013.01); G09G 5/14 (2013.01); G09G 2320/0252 (2013.01); G09G 2340/02 (2013.01); G09G 2340/04 (2013.01); G09G 2340/0407 (2013.01); G09G 2360/12 (2013.01); G09G 2360/18 (2013.01); G09G 2370/16 (2013.01);
Abstract

An apparatus and method are described for subdividing swap chains using partitions. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) to process graphics commands and responsively render a plurality of image frames; partition management logic to subdivide each of the image frames into at least two partitions and to designate each partition in each image frame as being in a front buffer or in a back buffer; the GPU to perform rendering operations to partitions designated as being in the back buffer; and a display link to concurrently perform a scan-out of scan lines from partitions designated as being in a front buffer.


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