The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Jul. 01, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kermin Fleming, Hudson, MA (US);

Kent D. Glossop, Merrimack, NH (US);

Simon C. Steely, Jr., Hudson, NH (US);

Samantika S. Sury, Westford, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0802 (2016.01); H03K 19/177 (2006.01); G06F 17/50 (2006.01); G11C 7/10 (2006.01); G06F 15/78 (2006.01); G06F 15/80 (2006.01); G11C 8/12 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G06F 17/505 (2013.01); G11C 7/1012 (2013.01); H03K 19/1776 (2013.01); H03K 19/17736 (2013.01); G06F 15/7867 (2013.01); G06F 15/8015 (2013.01); G11C 8/12 (2013.01); G11C 2207/2245 (2013.01); H03K 19/1778 (2013.01); H03K 19/17756 (2013.01); H03K 19/17764 (2013.01); H03K 19/17776 (2013.01);
Abstract

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In an embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an atomic operation when an incoming operand set arrives at the plurality of processing elements.


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