The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

May. 31, 2017
Applicant:

Cavium, Llc, Santa Clara, CA (US);

Inventors:

Shubhendu Sekhar Mukherjee, Southborough, MA (US);

Isam Wadih Akkawi, Santa Clara, CA (US);

David Asher, Sutton, MA (US);

Michael Bertone, Marlborough, MA (US);

David Albert Carlson, Haslet, TX (US);

Bradley Dobbie, Cambridge, MA (US);

Richard Eugene Kessler, Northborough, MA (US);

Assignee:

Cavium, LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/30 (2018.01); G06F 9/52 (2006.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3009 (2013.01); G06F 9/3004 (2013.01); G06F 9/30072 (2013.01); G06F 9/30079 (2013.01); G06F 9/3834 (2013.01); G06F 9/4881 (2013.01); G06F 9/526 (2013.01); G06F 9/528 (2013.01); G06F 9/546 (2013.01);
Abstract

Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread. Prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor is preserved. The selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.


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