The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2019
Filed:
Feb. 03, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Kamlesh R. Pillai, Gujarat, IN;
Gurpreet S. Kalsi, Bangalore, IN;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/483 (2006.01); G06F 7/556 (2006.01); H03M 7/24 (2006.01); G06F 7/499 (2006.01); G06F 7/552 (2006.01); H03M 7/30 (2006.01); G06F 7/523 (2006.01); G06F 1/03 (2006.01);
U.S. Cl.
CPC ...
G06F 7/4833 (2013.01); G06F 1/0307 (2013.01); G06F 7/49915 (2013.01); G06F 7/5235 (2013.01); G06F 7/556 (2013.01); G06F 7/5525 (2013.01); H03M 7/24 (2013.01); H03M 7/3064 (2013.01); G06F 7/483 (2013.01); G06F 2207/3884 (2013.01);
Abstract
Implementations of the disclosure provide logarithm and anti-logarithm operations on a hardware processor based on linear piecewise approximation. An example processor includes a piece wise linear log approximation circuit that receives an input of a floating-point number comprising a sign, an exponent and a mantissa. The piece wise linear log approximation circuit approximates a fractional portion of a fixed point number using a linear approximation of the mantissa of the floating-point number. The piece wise linear log approximation circuit also derives an integer from the exponent.