The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2019
Filed:
Jan. 26, 2017
Dspace Digital Signal Processing and Control Engineering Gmbh, Paderborn, DE;
László Juhász, Deggendorf, DE;
Jesse Lakemeier, Hamburg, DE;
dSPACE digital signal processing and control engineering Gmbh, Paderborn, DE;
Abstract
A method for automated configuration of a tester equipped for testing a control unit. A first and second model of technical systems being executed in the tester. The execution of the models taking place periodically with defined sampling rates. An FPGA executes the first and/or the second model and a CPU executes the first or the second model. A first individual sampling rate is allocated for the first model and a second individual sampling rate is allocated for the second model. The first model is assigned for execution on either the CPU or the FPGA and the second model is assigned for execution on either the CPU or the FPGA. The tester is automatically configured for execution of the first model with the first allocated sampling rate on the FPGA or the CPU and of the second model with the second allocated sampling rate on the FPGA or the CPU.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile