The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Dec. 01, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Kilho Lee, Busan, KR;

Gwanhyeob Koh, Seoul, KR;

Hongsoo Kim, Seongnam-si, KR;

Junhee Lim, Seoul, KR;

Chang-Hoon Jeon, Goyang-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); H01L 27/24 (2006.01); G11C 11/00 (2006.01); H01L 45/00 (2006.01); H01L 27/11573 (2017.01); G11C 13/00 (2006.01); H01L 27/22 (2006.01); G11C 11/16 (2006.01); H01L 43/08 (2006.01); H01L 49/02 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); G11C 5/025 (2013.01); G11C 11/005 (2013.01); G11C 11/1659 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01); H01L 27/224 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 28/20 (2013.01); H01L 43/08 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); G11C 11/161 (2013.01); G11C 13/0002 (2013.01); G11C 13/0004 (2013.01); G11C 2213/79 (2013.01);
Abstract

Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.


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