The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Jan. 15, 2018
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Cheng-Ta Yang, Taichung, TW;

Lu-Ping Chiang, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/11521 (2017.01); H01L 27/11546 (2017.01); H01L 27/11529 (2017.01); H01L 29/49 (2006.01); H01L 27/11524 (2017.01); H01L 27/11536 (2017.01); H01L 27/11539 (2017.01); H01L 27/11541 (2017.01); H01L 27/11543 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11536 (2013.01); H01L 27/11539 (2013.01); H01L 27/11541 (2013.01); H01L 27/11543 (2013.01); H01L 27/11546 (2013.01); H01L 29/49 (2013.01);
Abstract

A method for manufacturing a semiconductor memory device including following steps is provided. A substrate having a first region, a second region, and a third region is provided. A first stack structure is formed on the first region. A second stack structure is formed on the second region. A third stack structure is formed on the third region. A first mask layer is formed on the substrate to cover the third stack structure. A first ion implantation process is performed, so that a second floating gate and a second control gate in the second stack structure are changed to a first conductive type. A second mask layer formed on the substrate to cover the first and second stack structures. A second ion implantation process is performed, so that a third floating gate and a third control gate in the third stack structure are changed as a second conductive type.


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