The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Jul. 24, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Dylan R. Macmaster, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); H01L 27/108 (2006.01); G11C 11/401 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10823 (2013.01); G11C 11/401 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 27/10855 (2013.01); H01L 27/10885 (2013.01);
Abstract

An integrated circuitry construction comprises a substrate comprising conductive nodes of integrated circuitry. A conductive line structure is above the conductive nodes. Elevationally-extending conductive vias are spaced longitudinally along the conductive line structure. The conductive vias individually directly electrically couple the conductive line structure to individual of the conductive nodes. The conductive line structure comprises conductive material directly electrically coupled to the conductive vias and extending between immediately-longitudinally-adjacent of the conductive vias. An upper insulative material is directly below the conductive material between the immediately-longitudinally-adjacent conductive vias. Doped or undoped semiconductor material directly is below the upper insulative material between the immediately-longitudinally-adjacent conductive vias. A lower insulative material is directly below the semiconductor material between the immediately-longitudinally-adjacent conductive vias. Other aspects, including method, are disclosed.


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