The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Jan. 11, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yasuo Satoh, Tsukuba, JP;

Tyler J. Gomm, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4076 (2006.01); H03K 3/017 (2006.01); H03K 23/00 (2006.01); H03M 7/16 (2006.01); G11C 29/02 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 29/023 (2013.01); H03K 3/017 (2013.01); H03K 23/005 (2013.01); H03M 7/16 (2013.01); H03K 19/21 (2013.01);
Abstract

Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.


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