The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2019
Filed:
Dec. 14, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventor:
Daniel Greenspan, Jerusalem, IL;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0897 (2016.01); G06F 12/08 (2016.01); G06F 12/0815 (2016.01); G06F 12/0846 (2016.01); G06F 12/0808 (2016.01); G06F 12/0811 (2016.01); G06F 12/0855 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0897 (2013.01); G06F 12/08 (2013.01); G06F 12/0815 (2013.01); G06F 12/0808 (2013.01); G06F 12/0811 (2013.01); G06F 12/0846 (2013.01); G06F 12/0855 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/608 (2013.01);
Abstract
In an embodiment, a processor includes at least one core and a first cache memory including a first plurality of sets having a first plurality of cache lines and associated metadata to store address information, recency information and a first indicator to indicate whether the cache line is associated with an oversubscribed set of a second cache memory. A first cache controller may be configured to base an eviction decision with regard to a first set of the first plurality of sets including a first cache line at least in part on the first indicator of the first cache line. Other embodiments are described and claimed.