The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Oct. 13, 2017
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Steven Woo, Saratoga, CA (US);

David A. Secker, San Jose, CA (US);

Ravindranath Kollipara, Palo Alto, CA (US);

Assignee:

Rambus Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/14 (2006.01); G06F 1/12 (2006.01); G06F 11/20 (2006.01); G06F 11/16 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1456 (2013.01); G06F 1/12 (2013.01); G06F 11/1666 (2013.01); G06F 11/2058 (2013.01); G06F 11/20 (2013.01); G06F 13/4234 (2013.01); G06F 2201/84 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.


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