The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Sep. 28, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sofia Pediaditaki, San Jose, CA (US);

Ethan Schuchman, Santa Clara, CA (US);

Rangeen Basu Roy Chowdhury, Santa Clara, CA (US);

Manjunath Shevgoor, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/30 (2018.01); G06F 12/0846 (2016.01); G06F 12/128 (2016.01); G06F 9/52 (2006.01); G06F 12/0811 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3004 (2013.01); G06F 9/30036 (2013.01); G06F 9/524 (2013.01); G06F 12/0811 (2013.01); G06F 12/0848 (2013.01); G06F 12/128 (2013.01); G06F 2212/282 (2013.01); G06F 2212/283 (2013.01); G06F 2212/621 (2013.01);
Abstract

Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.


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