The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2019
Filed:
Aug. 10, 2017
Applicant:
SK Hynix Inc., Gyeonggi-do OT, KR;
Inventors:
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); H04L 1/20 (2006.01); G06F 11/07 (2006.01); G11C 29/50 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 29/02 (2006.01); G11C 29/52 (2006.01); G06F 11/10 (2006.01); G11C 29/56 (2006.01); G11C 16/04 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
H04L 1/203 (2013.01); G06F 11/076 (2013.01); G06F 11/1012 (2013.01); G11C 11/5642 (2013.01); G11C 16/349 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 29/50004 (2013.01); G11C 29/52 (2013.01); G11C 16/0483 (2013.01); G11C 29/56008 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01); G11C 2029/5004 (2013.01);
Abstract
An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a BER predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct NAND read and generate NAND data; decode in accordance with the NAND data and generate decoder information by the decoder; predict a BER in accordance with at least the decode information by the BER predictor; and evaluate the predicted BER and generate evaluation result by the BER predictor.