The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Apr. 18, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Jin Ook Song, Seoul, KR;

Bong Il Park, Seongnam-si, KR;

Jae Gon Lee, Yongin-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/135 (2006.01); H03K 5/05 (2006.01); H03K 5/00 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 5/135 (2013.01); H03K 5/05 (2013.01); H03K 19/20 (2013.01); H03K 2005/00078 (2013.01); H03K 2005/00234 (2013.01);
Abstract

A clock generation circuit having a deskew function and a semiconductor integrated circuit device including the same are provided. The clock generation circuit includes a clock gating circuit configured to gate an input clock signal based on a first waveform signal to generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and to generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal having a period which is N times a period of the input clock signal.


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