The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Sep. 03, 2015
Applicant:

Hemlock Semiconductor Corporation, Hemlock, MI (US);

Inventors:

Jason L. Giardina, Freeland, MI (US);

James C. Mundell, Saginaw, MI (US);

Nathaniel C. McIntee-Chmielewski, Freeland, MI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 23/48 (2006.01); H01L 21/67 (2006.01); H01L 21/677 (2006.01); B08B 3/08 (2006.01); B08B 3/14 (2006.01); C30B 29/06 (2006.01); C30B 35/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02079 (2013.01); B08B 3/08 (2013.01); B08B 3/14 (2013.01); C30B 29/06 (2013.01); C30B 35/007 (2013.01); H01L 21/67028 (2013.01); H01L 21/67051 (2013.01); H01L 21/67721 (2013.01); H01L 21/67784 (2013.01); H01L 23/48 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A polysilicon chip reclamation assembly includes a polysilicon cleaning apparatus configured to clean a plurality of bodies of polysilicon. Also included is a plurality of polysilicon chips generated from the bodies of polysilicon during cleaning thereof, wherein each of the plurality of polysilicon chips has a longest dimensional length ranging from 0.1 mm to 25.0 mm. Further included is a polysilicon apparatus drain line configured to route the plurality of polysilicon chips from the polysilicon cleaning apparatus to a main chip drain line, wherein the main chip drain line is oriented at a downward slope away from the polysilicon apparatus drain line. Yet further included is a fluid source fluidly coupled to the main chip drain line and configured to inject a fluid into the main chip drain line to drive the plurality of polysilicon chips through the main chip drain line.


Find Patent Forward Citations

Loading…