The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Feb. 07, 2018
Applicant:

Bitmicro Networks, Inc., Fremont, CA (US);

Inventors:

Ricardo H. Bruce, Fremont, CA (US);

Cyrill Coronel Ponce, Malabon, PH;

Jarmie Dela Cruz Espuerta, Bacolod, PH;

Marlon Basa Verdan, Fremont, CA (US);

Assignee:

BiTMICRO Networks, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/20 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2007 (2013.01); G06F 11/202 (2013.01); G06F 11/2002 (2013.01); G06F 11/2005 (2013.01); G06F 11/2017 (2013.01); G06F 11/2023 (2013.01); G06F 11/2041 (2013.01); G06F 13/1605 (2013.01); G06F 13/4031 (2013.01);
Abstract

In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.


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