The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2019
Filed:
Apr. 17, 2017
Intel Corporation, Santa Clara, CA (US);
Deepak S. Vembar, Portland, OR (US);
Atsuo Kuwahara, Hillsboro, OR (US);
Chandrasekaran Sakthivel, Sunnyvale, CA (US);
Radhakrishnan Venkataraman, Folsom, CA (US);
Brent E. Insko, Portland, OR (US);
Anupreet S. Kalra, Folsom, CA (US);
Hugues Labbe, Folsom, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Michael Apodaca, Folsom, CA (US);
Kai Xiao, Santa Clara, CA (US);
Jeffery S. Boles, Folsom, CA (US);
Adam T. Lake, Portland, OR (US);
David M. Cimini, Orangevale, CA (US);
Balaji Vembu, Folsom, CA (US);
Elmoustapha Ould-Ahmed-Vall, Chanfler, AZ (US);
Jacek Kwiatkowski, Santa Clara, CA (US);
Philip R. Laws, Santa Clara, CA (US);
Ankur N. Shah, Folsom, CA (US);
Abhishek R. Appu, El Dorado Hills, CA (US);
Joydeep Ray, Folsom, CA (US);
Wenyin Fu, Folsom, CA (US);
Nikos Kaburlasos, Lincoln, CA (US);
Prasoonkumar Surti, Folsom, CA (US);
Bhushan M. Borole, Rancho Cordova, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.