The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Jun. 15, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Xia Li, San Diego, CA (US);

Jianguo Yao, Londonderry, NH (US);

Seung Hyuk Kang, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G11C 14/00 (2006.01); H01L 27/22 (2006.01); H01L 43/02 (2006.01); H04L 9/32 (2006.01); G11C 11/16 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0081 (2013.01); G11C 14/009 (2013.01); H01L 27/228 (2013.01); H01L 43/02 (2013.01); H04L 9/3278 (2013.01); G11C 11/161 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01);
Abstract

Physically unclonable function (PUF) memory employing static random access memory (SRAM) bit cells with added passive resistance are disclosed. Added passive resistance can enhance imbalance between transistors in the SRAM bit cell for improved PUF output reproducibility. Enhancing transistor imbalance can more fully skew the SRAM bit cell for increased PUF output reproducibility while still achieving the benefits of output randomness. In one exemplary aspect, added passive resistances in the SRAM bit cell are coupled to a drain of one or more pull-down N-type FETs (NFETs)) in one or more cross-coupled inverters in the SRAM bit cell to enhance imbalance between the inverters. Enhanced imbalance between the inverters increases sensitivity in the output voltage of the SRAM bit cell for a given change in input voltage resulting in greater skew of the SRAM bit cell for increased reproducibility.


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