The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Sep. 27, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Helia Naeimi, Santa Clara, CA (US);

Qi Zeng, Santa Clara, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/128 (2016.01); G06F 12/0891 (2016.01); G06F 12/0831 (2016.01); G06F 12/0811 (2016.01); G06F 12/123 (2016.01); G06F 12/121 (2016.01);
U.S. Cl.
CPC ...
G06F 12/128 (2013.01); G06F 12/0811 (2013.01); G06F 12/0831 (2013.01); G06F 12/0891 (2013.01); G06F 12/121 (2013.01); G06F 12/123 (2013.01); G06F 2212/283 (2013.01); G06F 2212/621 (2013.01);
Abstract

Provided are an apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line in a second memory device. An incoming cache line is read from the second memory device. A plurality of cache lines in the first memory device are processed to determine an eviction cache line of the plurality of cache lines in the first memory device having a least number of bits that differ from corresponding bits in the incoming cache line. Bits from the incoming cache line that are different from the bits in the eviction cache line are written to the eviction cache line in the first memory device.


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