The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Sep. 05, 2017
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Mark J. Beesley, Carmel Valley, CA (US);

Albert A. Onderick, II, Sunnyvale, CA (US);

Anne M. Mason, Palo Alto, CA (US);

Craig A. Gammel, Campbell, CA (US);

Shawn X. Arnold, Santa Cruz, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/00 (2006.01); H05K 3/42 (2006.01); H05K 1/14 (2006.01);
U.S. Cl.
CPC ...
H05K 1/112 (2013.01); H05K 3/0017 (2013.01); H05K 3/0047 (2013.01); H05K 3/425 (2013.01); H05K 1/11 (2013.01); H05K 1/14 (2013.01); H05K 2201/0959 (2013.01); H05K 2201/09227 (2013.01); H05K 2201/10734 (2013.01);
Abstract

Printed circuit boards having an increased density of vertical interconnect paths, as well as methods for their manufacture. One example may provide a printed circuit board having an increased density of vertical interconnect paths by forming a plurality of segmented vias. The segmented vias may extend through interior layers of the printed circuit board. The segmented vias may be formed of portions of vias in the interior layers of the printed circuit board. An area between three or more segmented vias may be filled with resin or other material or materials.


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