The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Oct. 15, 2018
Applicant:

Exar Corporation, Fremont, CA (US);

Inventors:

Vinit Jayaraj, Fremont, CA (US);

Pekka Ojala, Fremont, CA (US);

John Tabler, Fremont, CA (US);

Assignee:

Exar Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/01 (2006.01); H03K 17/16 (2006.01); H03K 17/30 (2006.01); H03K 17/06 (2006.01);
U.S. Cl.
CPC ...
H03K 17/302 (2013.01); H03K 17/063 (2013.01); H03K 2217/0018 (2013.01);
Abstract

In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.


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