The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2019
Filed:
Jan. 04, 2017
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/544 (2006.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11575 (2017.01); H01L 27/11578 (2017.01); H01L 29/10 (2006.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/544 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11578 (2013.01); H01L 29/1037 (2013.01); H01L 27/11565 (2013.01); H01L 2223/544 (2013.01); H01L 2223/54426 (2013.01);
Abstract
A vertical memory device includes a plurality of stacked structures, at least one inter-structure layer, and a channel structure. The plurality of stacked structures comprises a plurality of gate electrodes and a plurality of insulation film patterns that are alternately and repeatedly stacked on a substrate. At least one inter-structure layer is positioned between the two stacked structures adjacent to each other from among the plurality of stacked structures. A channel structure penetrates the plurality of stacked structures and the at least one inter-structure layer, the channel structure extending in the first direction, the channel structure being connected to the substrate.