The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Oct. 21, 2016
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Liang Chen, Shanghai, CN;

Shengfen Chiu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11524 (2017.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/764 (2006.01); H01L 27/11534 (2017.01); H01L 29/06 (2006.01); H01L 29/788 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); H01L 21/02164 (2013.01); H01L 21/02208 (2013.01); H01L 21/02271 (2013.01); H01L 21/02337 (2013.01); H01L 21/02359 (2013.01); H01L 21/31116 (2013.01); H01L 21/764 (2013.01); H01L 21/7682 (2013.01); H01L 27/11534 (2013.01); H01L 28/00 (2013.01); H01L 29/0649 (2013.01); H01L 29/7883 (2013.01);
Abstract

In some embodiments, a flash memory and a fabricating method thereof are provided. The method includes proving a substrate including multiple memory transistors and selecting transistors; forming a functional layer covering outer surfaces of the memory transistors and selecting transistors, and surfaces of the substrate between adjacent memory transistors and selecting transistors; performing a surface roughening treatment to the functional layer to provide a roughed surface of the functional layer that absorbs water; and forming a dielectric layer using a chemical vapor deposition (CVD) process, the absorbed water is evaporated from the functional layer during the CVD process to form an upward air flow that resists the deposition of the dielectric layer, such that air gaps are formed between adjacent memory transistors, and the dielectric layer covers top surfaces of the plurality of memory transistors and selecting transistors and fills gaps between each selecting transistor and corresponding adjacent memory transistor.


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