The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2019
Filed:
Apr. 26, 2018
Applicant:
Dialog Semiconductor (Uk) Limited, London, GB;
Inventor:
Ian Kent, Chippenham, GB;
Assignee:
Dialog Semiconductor (UK) Limited, London, GB;
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 24/96 (2013.01); H01L 21/4857 (2013.01); H01L 21/4864 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2224/214 (2013.01); H01L 2924/19106 (2013.01); H01L 2924/3511 (2013.01);
Abstract
A method to fabricate a reconstructed panel based fan-out wafer level package is described. A reconstructed wafer panel is provided comprising a plurality of individual dies encapsulated in a first molding compound. Interconnected metal redistribution layers (RDL) separated by PSV layers are formed on top surfaces of the plurality of individual dies. Thereafter, the reconstructed wafer panel is cut into a plurality of rectangular strips. Thereafter, backend processing is performed on each of the plurality of rectangular strips.