The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Dec. 21, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Yun-Rae Cho, Suwon-si, KR;

Sundae Kim, Hwaseong-si, KR;

Hyunggil Baek, Suwon-si, KR;

Namgyu Baek, Suwon-si, KR;

Seunghun Shin, Asan-si, KR;

Donghoon Won, Asan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/02 (2006.01); H01L 21/78 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/02675 (2013.01); H01L 21/78 (2013.01); H01L 23/585 (2013.01);
Abstract

A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.


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