The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

May. 22, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Daeik Kim, Del Mar, CA (US);

Jie Fu, Sunnyvale, CA (US);

Manuel Aldrete, Encinitas, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/82 (2006.01); H01L 21/00 (2006.01); H01L 23/552 (2006.01); H01L 23/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 23/66 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6627 (2013.01);
Abstract

Certain aspects of the present disclosure are directed to an integrated circuit (IC) package. The IC package generally includes an IC and a shielding sidewall disposed adjacent to the IC. In certain aspects, the IC comprises a first layer coupled to the shielding sidewall, a second layer comprising a first signal path, and a third layer disposed below the first layer and coupled to the shielding sidewall, wherein the second layer is disposed between the first layer and the third layer. In some cases, the IC also includes a plurality of vias configured to couple the first layer to the third layer, wherein at least a portion of the first signal path is disposed in an inner shielding region that spans from the first layer to the third layer and spans from the shielding sidewall to the plurality of vias.


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