The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Jan. 13, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yoshihisa Matsubara, Ibaraki, JP;

Takashi Ishigami, Ibaraki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/482 (2006.01); H01L 23/00 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 23/4824 (2013.01); H01L 23/5286 (2013.01); H01L 24/00 (2013.01); H01L 29/66795 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/45147 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An improvement is achieved in the performance of a semiconductor-device. The semiconductor device includes MISFETs formed in the upper surface of a substrate, a plurality of wiring layers stacked over the upper surface of the substrate, and a plurality of plugs each coupling two of the wiring layers to each other. The wiring layers located under the uppermost wiring layer include wires. The uppermost wiring layer includes a pad, an insulating film formed over the pad, and an opening extending through the insulating film and reaching the pad. The MISFETs and the wires overlap the opening in plan view. None of the plurality of plugs overlaps the opening in plan view.


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