The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Aug. 16, 2016
Applicant:

China Wafer Level Csp Co., Ltd., Suzhou, Jiangsu, CN;

Inventors:

Zhiqi Wang, Suzhou, CN;

Xianglong Liu, Suzhou, CN;

Yuanhao Xu, Suzhou, CN;

Assignee:

China Wafer Level CSP Co., Ltd., Suzhou, Jiangsu, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/24 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 23/24 (2013.01); H01L 27/14618 (2013.01); H01L 27/14687 (2013.01);
Abstract

A semiconductor chip package and a semiconductor chip packaging method are provided. The package includes: a semiconductor chip having a functional region, a protective substrate located on one side of the semiconductor chip and covering the functional region, and a support unit located between the protective substrate and the semiconductor chip and enclosing the functional region. The support unit includes an outer support member and an inner support member located inside the outer support member. A receiving cavity is formed between the inner support member, the semiconductor chip and the protective substrate. A hollow cavity is formed between the inner support member, the outer support member, the semiconductor chip and the protective substrate. The inner support member is provided with at least one first ventilating structure, through which the receiving cavity is in communication with the hollow cavity.


Find Patent Forward Citations

Loading…