The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2019
Filed:
Dec. 27, 2016
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Jagjot Kaur, Milpitas, CA (US);
Priyanka Dasgupta, Bangalore, IN;
Pratyush Aditya Kothamasu, Milpitas, CA (US);
Vivek Chickermane, Slaterville Springs, NY (US);
Assignee:
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 11/27 (2006.01);
U.S. Cl.
CPC ...
G06F 17/505 (2013.01); G06F 17/5045 (2013.01); G06F 11/27 (2013.01); G06F 2217/14 (2013.01);
Abstract
Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.