The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Sep. 29, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Tonia G. Morris, Irmo, SC (US);

Christopher P. Mozak, Beaverton, OR (US);

Christopher E. Cox, Placerville, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 11/4076 (2006.01); G11C 8/12 (2006.01); G11C 29/00 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0632 (2013.01); G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G11C 8/12 (2013.01); G11C 11/4076 (2013.01); G11C 29/00 (2013.01); G11C 29/028 (2013.01);
Abstract

A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.


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