The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Sep. 09, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bin Xing, Hillsboro, OR (US);

Mark W. Shanahan, Raleigh, NC (US);

Bo Zhang, Raleigh, NC (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0875 (2016.01); G06F 12/0893 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0605 (2013.01); G06F 3/061 (2013.01); G06F 3/0622 (2013.01); G06F 3/0631 (2013.01); G06F 3/0673 (2013.01); G06F 12/0875 (2013.01); G06F 12/0893 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/1056 (2013.01); G06F 2212/151 (2013.01); G06F 2212/45 (2013.01);
Abstract

Apparatuses, methods and storage medium associated with application execution enclave cache management, are disclosed herein. In embodiments, an apparatus may include one or more processors with supports for application execution enclaves; cache memory coupled with the one or more processors to be organized into a plurality of cache pages; and an exception handler to be operated by the one or more processors to handle cache page fault exceptions, wherein to handle cache page fault exceptions includes to handle a cache page fault triggered to request additional allocation of one or more cache pages to an execution enclave of an application. Other embodiments may be described and/or claimed.


Find Patent Forward Citations

Loading…