The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Oct. 13, 2017
Applicant:

Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai, CN;

Inventor:

Binghan Li, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/78 (2006.01); H01L 27/11521 (2017.01); H01L 21/266 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7883 (2013.01); H01L 21/266 (2013.01); H01L 21/28273 (2013.01); H01L 27/11521 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/7831 (2013.01);
Abstract

A flash memory structure, a memory array and a fabrication method thereof are disclosed. In the flash memory structure, an erase gate structure is formed between two floating gates, and a word line structure is formed on an outer side of each of the two floating gates, with an oxide layer formed between the word line structure and the substrate. The flash memory structure can be fabricated with a simple process. The memory array employing the flash memory structure is capable of erase operations by means of a voltage applied on erase gate lines and of read operations by means of a voltage applied on word lines. This enables read operations at a lower voltage with less power consumed by the memory array. In addition, the memory array is more efficient and more durable.


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