The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Sep. 05, 2017
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Rui Cheng, San Jose, CA (US);

Ziqing Duan, Sunnyvale, CA (US);

Milind Gadre, Santa Clara, CA (US);

Praket P. Jha, San Jose, CA (US);

Abhijit Basu Mallick, Fremont, CA (US);

Deenesh Padhi, Sunnyvale, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); C23C 16/30 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 21/3205 (2006.01); C23C 16/04 (2006.01); C23C 16/24 (2006.01); H01L 21/033 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28525 (2013.01); C23C 16/045 (2013.01); C23C 16/24 (2013.01); C23C 16/30 (2013.01); H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); H01L 21/02389 (2013.01); H01L 21/02488 (2013.01); H01L 21/02494 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/0337 (2013.01); H01L 21/3105 (2013.01); H01L 21/32055 (2013.01); H01L 21/02592 (2013.01); H01L 21/02639 (2013.01); H01L 21/02642 (2013.01);
Abstract

Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon layers on a semiconductor substrate. In one implementation, a method of forming a boron-doped amorphous silicon layer on a substrate is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a boron-doped amorphous silicon layer on the patterned features and the exposed upper surface of the substrate and selectively removing the boron-doped amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the boron-doped amorphous silicon layer.


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