The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Jun. 29, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Anupama A. Thaploo, Folsom, CA (US);

Bhushan Borole, Rancho Cordova, CA (US);

Muhammad M. Khellah, Tigard, OR (US);

Pascal A. Meinerzhagen, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G01R 31/318541 (2013.01); G11C 7/225 (2013.01); G11C 7/227 (2013.01);
Abstract

Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.


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