The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Apr. 02, 2018
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Chih-Chun Chen, Taipei, TW;

Chun-Hung Lin, Hsinchu, TW;

Cheng-Da Huang, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/32 (2006.01); G11C 11/56 (2006.01); G11C 7/22 (2006.01); H01L 27/06 (2006.01); H01L 27/112 (2006.01); G06F 21/73 (2013.01); G11C 7/06 (2006.01); G11C 7/12 (2006.01); G11C 7/24 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); G11C 16/34 (2006.01); G11C 29/44 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); H02H 9/04 (2006.01); G06F 7/00 (2006.01); H04L 9/08 (2006.01); G11C 16/06 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G06F 7/00 (2013.01); G06F 21/73 (2013.01); G11C 7/062 (2013.01); G11C 7/12 (2013.01); G11C 7/24 (2013.01); G11C 11/5642 (2013.01); G11C 16/045 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/34 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); G11C 29/44 (2013.01); H01L 27/0629 (2013.01); H01L 27/11206 (2013.01); H02H 9/04 (2013.01); H04L 9/0866 (2013.01); G11C 7/06 (2013.01); G11C 16/06 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01);
Abstract

A sensing circuit includes a sensing stage. The sensing stage includes a voltage clamp, a P-type transistor and an N-type transistor. The voltage clamp receives a first power supply voltage and generates a second power supply voltage. The source terminal of the P-type transistor receives the second power supply voltage. The gate terminal of the P-type transistor receives a cell current from a selected circuit of a non-volatile memory. The drain terminal of the N-type transistor is connected with the drain terminal of the P-type transistor. The gate terminal of the N-type transistor receives a bias voltage. The source terminal of the N-type transistor receives a ground voltage. In a sensing period, the second power supply voltage from the voltage clamp is fixed and lower than the first power supply voltage.


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