The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Mar. 31, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Berkin Akin, Hillsboro, OR (US);

Rajat Agarwal, Beaverton, OR (US);

Jong Soo Park, Santa Clara, CA (US);

Christopher J. Hughes, Santa Clara, CA (US);

Chiachen Chou, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0888 (2016.01); G06F 12/0811 (2016.01); G06F 12/04 (2006.01); G06F 12/0831 (2016.01); G06F 12/0886 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0888 (2013.01); G06F 12/04 (2013.01); G06F 12/0811 (2013.01); G06F 12/0831 (2013.01); G06F 12/0886 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/283 (2013.01); G06F 2212/6046 (2013.01);
Abstract

In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.


Find Patent Forward Citations

Loading…