The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2019
Filed:
Sep. 11, 2018
Applicant:
Invensas Corporation, San Jose, CA (US);
Inventor:
William C. Plants, Campbell, CA (US);
Assignee:
Invensas Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G11C 5/02 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/00 (2006.01); H03M 13/29 (2006.01); G11C 5/04 (2006.01); G11C 11/401 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 11/1012 (2013.01); G06F 11/1076 (2013.01); G11C 5/025 (2013.01); G11C 29/42 (2013.01); G11C 29/4401 (2013.01); G11C 29/52 (2013.01); G11C 29/783 (2013.01); H03M 13/2906 (2013.01); G11C 5/04 (2013.01); G11C 11/401 (2013.01);
Abstract
The invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing RAID-style error correction to increase the reliability of the stacked memory devices.