The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Jan. 25, 2017
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

William H. Radke, Los Gatos, CA (US);

Tommaso Vali, Latina, IT;

Michele Incarnati, Gioia Dei Marsi, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1048 (2013.01); G06F 3/064 (2013.01); G06F 3/0604 (2013.01); G06F 3/0608 (2013.01); G06F 3/0629 (2013.01); G06F 3/0631 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G06F 11/1072 (2013.01); G06F 12/0207 (2013.01); G06F 12/0646 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 29/52 (2013.01);
Abstract

A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block.


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