The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2019

Filed:

Jan. 04, 2018
Applicant:

Nustorage Technology Co., Ltd., Apia, WS;

Inventors:

Fu-Chou Liu, Hsin-Chu County, TW;

Yung-Tin Chen, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); G11C 19/28 (2006.01); G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1062 (2013.01); G11C 11/223 (2013.01); G11C 19/282 (2013.01); H01L 29/516 (2013.01); H01L 29/66007 (2013.01);
Abstract

A field effect transistor, a memory element, and a manufacturing method of a charge storage structure are provided. The memory element includes a plurality of field effect transistors, and each of the field effect transistors includes a substrate, a source region, a drain region, a gate conductive layer, and a charge storage structure. Both the source region and the drain region are located in the substrate and connected to an upper surface of the substrate. The source and drain regions are spaced apart from each other to define a channel region therebetween. The gate conductive layer is disposed over the upper surface and overlaps with the channel region. The charge storage structure disposed between the gate conductive layer and the channel region includes a ferroelectric material and a paraelectric material so that the charge storage structure has better capability of trapping charges and a higher switching speed.


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