The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2019
Filed:
Mar. 31, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Berkin Akin, Hillsboro, OR (US);
Rajat Agarwal, Beaverton, OR (US);
Jong Soo Park, Santa Clara, CA (US);
Christopher J. Hughes, Santa Clara, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0888 (2016.01); G06F 12/0811 (2016.01); G06F 12/0831 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0888 (2013.01); G06F 12/0811 (2013.01); G06F 12/0831 (2013.01); G06F 2212/283 (2013.01); G06F 2212/6046 (2013.01); G06F 2212/621 (2013.01);
Abstract
In one embodiment, a processor includes: a core including a decode unit to decode a memory access instruction having a no-locality hint to indicate that data associated with the memory access instruction has at least one of non-spatial locality and non-temporal locality; and a locality controller to determine whether to override the no-locality hint based at least in part on one or more performance monitoring values. Other embodiments are described and claimed.