The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2019

Filed:

Jul. 26, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jayashankar Bharadwaj, Saratoga, CA (US);

Nalini Vasudevan, Sunnyvale, CA (US);

Albert Hartono, Santa Clara, CA (US);

Sara S. Baghsorkhi, San Jose, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 8/41 (2018.01); G06F 9/06 (2006.01); G06F 9/30 (2018.01); G06F 9/44 (2018.01);
U.S. Cl.
CPC ...
G06F 8/4441 (2013.01); G06F 8/443 (2013.01); G06F 8/452 (2013.01); G06F 9/06 (2013.01); G06F 9/30 (2013.01); G06F 9/44 (2013.01);
Abstract

Methods and systems to convert a scalar computer program loop having loop-carried dependences into a vector computer program loop are disclosed. One such method includes, at runtime, identifying, by executing an instruction with one or more processors, a first loop iteration that cannot be executed in parallel with a second loop iteration due to a set of conflicting scalar loop operations. The first loop iteration is executed after the second loop iteration. The method also includes sectioning, by executing an instruction with one or more processors, a vector loop into vector partitions including a first vector partition. The first vector partition executes consecutive loop iterations in parallel and the consecutive loop iterations start at the second loop iteration and end before the first loop iteration.


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