The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Nov. 01, 2017
Applicant:

Sumitomo Electric Device Innovations, Inc., Yokohama-shi, JP;

Inventors:

Shuichi Kubota, Yokohama, JP;

Masahiro Hirayama, Yokohama, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/04 (2006.01); H04B 10/516 (2013.01); G02B 19/00 (2006.01); G02B 27/28 (2006.01); G02B 27/30 (2006.01); H01S 5/022 (2006.01); H01S 5/068 (2006.01); H01S 5/00 (2006.01); H01S 5/042 (2006.01); G02B 6/42 (2006.01);
U.S. Cl.
CPC ...
H04B 10/516 (2013.01); G02B 19/0009 (2013.01); G02B 19/0028 (2013.01); G02B 19/0057 (2013.01); G02B 27/283 (2013.01); G02B 27/30 (2013.01); H01S 5/02276 (2013.01); H01S 5/06808 (2013.01); G02B 6/4206 (2013.01); G02B 6/4214 (2013.01); G02B 6/4246 (2013.01); G02B 6/4292 (2013.01); H01S 5/0078 (2013.01); H01S 5/02236 (2013.01); H01S 5/02284 (2013.01); H01S 5/0427 (2013.01); H01S 2301/02 (2013.01);
Abstract

An optical module installed within an optical transmitter apparatus is disclosed. The optical module provides an electrically insulating carrier, a semiconductor element, and a capacitor. The carrier provides a ground pattern and a bias pad. The ground pattern mounts the capacitor and the semiconductor element thereon. The bias pad is electrically isolated from the ground pattern thereby forming a parasitic capacitor against the ground pattern. The optical module further includes at least two bonding wires among a first bonding wire connecting the semiconductor element with the bias pad, a second bonding wire connecting the bias pad with the capacitor, and an additional bonding wire connecting the capacitor with the semiconductor element. The semiconductor element is supplied with a bias current through the at least two bonding wires.


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