The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Nov. 13, 2017
Applicant:

Samsung Electro-mechanics Co., Ltd., Suwon-si, KR;

Inventors:

Byeong Hak Jo, Suwon-si, KR;

Jeong Hoon Kim, Suwon-si, KR;

Jong Ok Ha, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 1/02 (2006.01); H03F 3/21 (2006.01); H03F 3/189 (2006.01); H03F 3/24 (2006.01);
U.S. Cl.
CPC ...
H03F 1/02 (2013.01); H03F 3/189 (2013.01); H03F 3/21 (2013.01); H03F 3/24 (2013.01); H03F 3/45475 (2013.01); H03F 2200/102 (2013.01); H03F 2200/241 (2013.01); H03F 2200/375 (2013.01); H03F 2200/451 (2013.01); H03F 2203/45102 (2013.01);
Abstract

An envelope-tracking current bias circuit includes a first rectifying circuit, a second rectifying circuit, and a first arithmetic circuit. The first rectifying circuit is configured to detect an envelope of an input signal, and provide an envelope detection signal comprising a first direct current (DC) offset voltage. The second rectifying circuit is configured to provide a second DC offset voltage corresponding to the first DC offset voltage. The first arithmetic circuit is configured to provide an envelope signal in which the first DC offset voltage is reduced through subtraction between the envelope detection signal and the second DC offset voltage.


Find Patent Forward Citations

Loading…